The present invention relates to a semiconductor memory device, and more particularly to an electrostatic discharge protection device having a low junction capacitance and operational voltage for protecting an internal circuit from an electrostatic current.
A typical semiconductor memory device includes an electrostatic discharge protection device between an input/output pad and an internal circuit in order to prevent the internal circuit from being influenced by the electrostatic current.
Design trends in the semiconductor devices call for manufacturing semiconductor devices that achieve higher speeds and that are highly integrated. In these high speed, highly intergraded semiconductor devices, a low pin capacitance is required, and the gate oxide of the semiconductor device is very thin. In particular, the pin capacitance may adversely influence the input/output transfer speed and perseverance of the signal, and thus it is necessary to reduce the pin capacitance for high-speed devices.
The pin capacitance makes up more than 50% of the total junction capacitance of a semiconductor device, and a considerable portion of the pin capacitance consists of the parasitic junction capacitance of the electrostatic discharge protection element connected to the input/output pad.
Therefore, the junction capacitance of the electrostatic protection device must be reduced by improving the area suitable for high-speed and highly integrated products, and the operational speed of the electrostatic protection device must be increased in order to protect the thin gate oxide layer of the internal circuit device.
Referring to FIG. 1, a conventional electrostatic discharge protection device includes a P-type diode 104 connected between the input/output pad 100 and the power supply voltage line VCC 102, an N-type diode 105 connected between the input/output pad 100 and the ground voltage line VSS 103, a CDM transistor protection resistor 106 connected between the input/output pad 100 and the internal circuit 108, a CDM transistor 107 connected between the internal circuit 108 and the ground voltage line VSS 103, and a power clamp 109 connected between the power supply voltage line VCC 102 and the ground voltage line VSS 103.
Referring to FIG. 2A, the P-type diode 104 has a P-type impurity region 202 and an N-type impurity region 204 formed within an N-well region 201, and an element isolation layer 203 interposed between the P-type impurity region 202 and the N-type impurity region 204. The P-type impurity region 202 is connected to the input/output pad 100, and the N-type impurity region 204 is connected to the power supply voltage line VCC 102.
Referring to FIG. 2B, the N-type diode 105 has an N-type impurity region 212 and an P-type impurity region 214 formed within a P-well region 211, and an element isolation layer 213 interposed between the N-type impurity region 212 and the P-type impurity region 214. The N-type impurity region 212 is connected to the input/output pad 100, and the P-type impurity region 214 is connected to the ground voltage line VSS 103.
Further, as shown in FIG. 3, an N-type guard ring 220 is disposed adjacent to the N-type diode 105 to prevent latch-up between the input/output pad 100 and adjacent circuits. More specifically, the N-type guard ring 220 has an N-type impurity region 224 formed within the N-well region 222, and the N-type impurity region 224 is connected to an external voltage line VDD 226. Reference numeral 215 is an element isolation layer that separates the P-type impurity region 214 from the N-type impurity region 224.
Although the conventional electrostatic discharge protection device has a small junction region when using the P-type diode 104 and the N-type diode 105, a problem occurs, in that the conventional electrostatic discharge protection device cannot effectively protect the gate oxide of the internal circuit 108 if the operational speed of the power clamp 109 is low.
Further, the conventional electrostatic discharge protection device discharges negative electrostatic currents flowing from the input/output pad 100 from the power supply voltage pad VCC 102, through the power clamp 109 and then the N-type diode 105, to the input/output pad 100. In this case, if the power clamp 109 does not operate rapidly, a parasitic NPN bipolar transistor T1 present between the N-type guard ring 220 and the N-type diode 105 operates as shown in FIG. 3. As a result, an undesirable electrostatic discharge path is formed. Therefore, failure can occur between the vulnerable N-type guard ring 220 and the P-type impurity region 214.